Worth a Read
Power Delivery Is Moving Onto the Package
Chipstrat reads ADI's $1.5bn Empower deal and PowerLattice's raise as one bet: voltage regulation is migrating onto the package, micrometres under the compute die. The cut, and where it meets the Closelooknet build-out frameworks.
Source: Chipstrat (Substack) Read the original →
Chipstrat's read of last week's chip-power news is that voltage regulation has quietly become a packaging problem. The trigger was two transactions pointing the same way: ADI agreeing to buy Empower Semiconductor for $1.5bn in cash, and the startup PowerLattice closing a $25m round backed by Playground Global and Celesta Capital. Chipstrat reads both as bets that the regulator — long a motherboard component sitting centimetres from the chip — now has to move onto the package itself, micrometres beneath the compute die.
The forcing function is current. A Vera Rubin–class XPU is specified to pull on the order of 3,286 amps at 0.7 volts, against roughly 1,000 amps for a Hopper H100; at those levels the resistive losses along the long path from a board-level regulator stop being a rounding error. Chipstrat puts system efficiency near 66% for today's one-kilowatt parts and falling toward 42% at the five-kilowatt GPUs on the roadmap. The proposed fix is an integrated voltage regulator built into the substrate, directly under the load — PowerLattice's “Rainier” micro-IVR claims to cut effective compute-power loss by more than half — which Chipstrat frames as a new merchant “IVR socket” opening up inside the package.
“The only way out is to shorten the high-current portion of the path.”
Chipstrat
That sentence is why this reads as a build-out story rather than a power-supply story. When the fix is geometric — move the regulator micrometres from the die because nothing else clears the losses — power delivery stops being a board-level line item and takes a seat at the advanced-packaging table, next to the HBM stack and the interposer. The value migrates into the package, and so does the pricing power.
Where it meets the Closelooknet frameworks
This is a migration Closelooknet already tracks from two angles. It is the packaging bottleneck read and the power constraint read converging on the same square millimetre of substrate — the real estate that already hosts CoWoS and the memory stack now has to host a voltage regulator too. The Build-Out semiconductors that capture this sit in Rubin and Euro-AI, and Chipstrat's piece is a clean supply-side tape on the trend: the more functions move into the package, the more the bottleneck — and the margin — concentrates there.
Closelooknet keeps this as a market-diary observation, not a recommendation — the signal is where value is migrating in the stack, not a call on ADI, Empower or any single name.
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