Modern AI chips are not monolithic — they are systems of multiple dies (compute, memory, I/O) connected through advanced packaging. NVIDIA's Blackwell GPU uses TSMC's CoWoS (Chip-on-Wafer-on-Substrate) to bond compute dies with HBM3E memory stacks. Without this packaging step, the chip doesn't function.
The problem: advanced packaging capacity is far more constrained than wafer fabrication. TSMC can fabricate more wafers than it can package. This makes packaging the throughput limiter for the entire AI chip supply chain. Every additional NVIDIA GPU requires packaging capacity that doesn't exist yet.
TSMC controls the majority of CoWoS capacity and is investing heavily to expand — but new capacity takes 18-24 months to come online. Pricing power is strong.
BESI is the leading supplier of hybrid bonding equipment — the next-generation packaging technology that enables higher-density chip-to-chip connections. Hybrid bonding is essential for HBM4 and future architectures. BESI's order book is a forward indicator for packaging capacity expansion.
ASE Technology is the largest OSAT (outsourced semiconductor assembly and test) provider, handling advanced packaging for clients who can't access TSMC's CoWoS.
Substrate makers (Ibiden, Shinko, Samsung Electro-Mechanics) provide the organic and glass substrates that form the base layer of advanced packages. Substrate supply is another constraint within the constraint.
Packaging companies trade at lower multiples than compute companies (NVIDIA, AMD) despite having comparable bottleneck positioning. This valuation gap exists because packaging is less visible to generalist investors. Closelook's Constraint Sectors thesis suggests this gap narrows as the market recognizes that AI chip supply is packaging-limited, not fabrication-limited.
The packaging bottleneck is one of Closelook's highest-conviction constraint themes. It's tracked through the Silicon layer of the Functional Index, with BESI's order book serving as a leading indicator for capacity expansion.
Functional Index — Silicon Layer →Constraint Sectors →AI Chip Buildout Dossier →